Programming a 144-computer chip to minimize power
youtubeChip/computer design
About
the GA144 chips
A matrix of 144 "computers" on a ~5mm chip
The whole chip
96gips, 550milliwatts, 15µw idle
Each one of the 144 computers
1ns/instruction -> 666mips
4milliwatts of power running -> 7picojoules/instruction
100nanowatts idle
Relevant, recent, design concerms
Interested in reducing power consumption both for portable devices and for server farms
Computer parameters
18 bits/word
4 instructions/word
A 32 instruction (5-bit) ISA (instruction set architecture)
64 word RAM, 5nano second access
2 x 9-deep push-down stacks
t
top of stack register
s
parameter stack
r
return stack
3 address registers a, b (registers) p (program counter)
Can communicate with 4 "neighbours" (up, down, left, right)
Programming
Input/output ports from neighbour computers are memory-mapped, so the computer can "jump" to that "neighbours" address, which means that they'll wait for a word from that neighbour and execute it.
See
Reading between communication lines is "blocking" and takes no energy (100nanoW)
Programmed using
Optimum programming
Fast
Minimize instructions executed
Use all slots on word
Fetches @ and stores ! should be used early in word so address bus can be used to prefetch the next instruction word
Position code to allow jump in slot 2
Slot 2 allows jumps inside a 8-word page
Use of a better algorithm
Compact
minimize instructions
avoid literals
dup or (duplicate, exclusive or) instead of 0
A literal is a fetch from the address and the p register
prefer unext to next
initialize registers, stacks from port
better algorithm
Low energy
measure with µa meter (see)
low duty cycle
wait on neighbour, pin 0 power
avoid timing loops
zero stacks and drop garbage
position loop to minimize address bit change
avoid literals
better algorithm