// Code generated by Icestudio 0.5.0
// Mon, 22 Mar 2021 22:15:57 GMT

`default_nettype none

module main #(
 parameter v2fb628 = 19
) (
 input vaef181,
 input vclk,
 output [7:0] v31451a
);
 localparam p1 = v2fb628;
 wire [0:7] w0;
 wire w2;
 wire w3;
 wire w4;
 assign v31451a = w0;
 assign w3 = vaef181;
 assign w4 = vclk;
 v6a5074 #(
  .v100e1b(p1)
 ) vbb0b73 (
  .v2efea4(w2),
  .v0daa9e(w4)
 );
 main_v243a90 v243a90 (
  .value(w0),
  .clk(w2),
  .btn(w3)
 );
endmodule

module v6a5074 #(
 parameter v100e1b = 22
) (
 input v0daa9e,
 output v2efea4
);
 localparam p2 = v100e1b;
 wire w0;
 wire w1;
 assign v2efea4 = w0;
 assign w1 = v0daa9e;
 v6a5074_vac7386 #(
  .N(p2)
 ) vac7386 (
  .clk_out(w0),
  .clk_in(w1)
 );
endmodule

module v6a5074_vac7386 #(
 parameter N = 0
) (
 input clk_in,
 output clk_out
);
 //-- Number of bits of the prescaler
 //parameter N = 22;

 //-- divisor register
 reg [N-1:0] divcounter;

 //-- N bit counter
 always @(posedge clk_in)
   divcounter <= divcounter + 1;

 //-- Use the most significant bit as output
 assign clk_out = divcounter[N-1];
endmodule

module main_v243a90 (
 input clk,
 input btn,
 output [7:0] value
);
 reg [7:0] value;

 always @(posedge clk) begin
   if (btn == 1)
     value <= value - 1;
   else
     value <= value + 1;
 end


endmodule